This invention relates generally to a decoder for use in integrated circuit memories and the like and, more particularly to a redundant decoder for use in conjunction with a predecoded addressing scheme.
In the manufacture of integrated circuit memories (e.g. MOS memories), many devices fail due to the failure of a single decoding bit. As a result, redundant decoding has become common, and its economic advantage (i.e. higher yield) is well established. It has since been established that the use of predecoders greatly reduces the complexity of the memory's decoding function resulting in the occupation of less space on the semiconductor die. That is, instead of utilizing a decoding scheme wherein all address lines are applied to a single large decoding stage, certain ones of the address lines are applied to a plurality of predecoding gates, the outputs of which are coupled to the inputs of a smaller plurality of decoding gates. The outputs of the decoding gates then control the memory's bit lines.
Since existing redundancy techniques are tailored for use in non-predecoded addressing schemes, a need exists for an improved redundant decoder which predecodes the addresses.